Agp System Architecture

€ 52,99
Besorgung - Lieferbarkeit unbestimmt
Oktober 1999





About This Book. The MindShare Architecture Series. Cautionary Note. Organization of This Book. Who This Book Is For. Prerequisite Knowledge. Documentation Conventions. Visit Our Web Site. We Want Your Feedback. 1. The 3D Graphics Challenge. 3D Graphics Compute- and Memory-Intensive. 2. PCI/AGP Adapter Overview. System Overview. Local Versus Main Memory. PCI Graphics Adapter. Intro To AGP Graphics Adapter. 3. AGP Enumeration and Configuration. Example Enumeration/Configuration of AGP. Host/PCI Bridge PCI Bus 0, Device 0, Function 0. AGP Enable/Disable Bit. Discovering Host/PCI Bridge's AGP Register Set. NB Connects To AGP Bus via PCI-to-PCI Bridge. PCI-to-PCI Bridge's Configuration Registers. Assigning AGP Bus Number. Device At Other End of Bus Needn't Be a Graphics Adapter. Discovering AGP Graphics Adapter. Discovering Adapter's AGP Capability Register Set. Setting Up Adapter's BAR Registers. 4. AGP Memory Allocation and Usage. Introduction To Dynamic Memory Allocation. AGP Aperture Implementation. 5. Windows Use of AGP. Intro to Windows Software Environment. BIOS Initialization Requirements. Operating System Initialization Requirements. 6. PCI Protocol Review. Some Basic Rules For Both Reads and Writes. Example Single Data Phase Read. Example Burst Read. Treatment of Byte Enables During Read or Write. Performance During Read Transactions. Example Single Data Phase Write Transaction. Example Burst Write Transaction. Performance During Write Transactions. PCI Is Not An Efficient Bus. 7. Intro to AGP Concepts & Terminology. Decoupling Address and Data Phases Optimizes Bus Usage. Bus Arbitration. Issuing Transaction Requests. PCI Bus Master Can Write to AGP Adapter's Local Memory. GART Support for PCI Masters Is Optional. Monochrome Device Adapter (MDA) Support. Some Terminology. 8. The Signal Groups. Required Versus Optional Features. PCI Target Latency Rules Don't Apply to North Bridge. AGP Graphics Adapter Cannot Use Subtractive Decode. North Bridge/AGP Adapter Interconnect Examples. Introduction To Signal Description. AGP Clock Signal. Reset (RST#). The Signaling Environment (I/O Voltage). Where Is the AGP Bus Arbiter Located? Signal Usage In AGP Transactions. Signal Usage In PCI Transactions. Signal Usage in Fast Write Transactions. Special Overflow Prevention Signals. Unimplemented PCI Signals. Interrupt Generation. Error Reporting. USB-Related Signals. Power Management. Signal Types. Pull-Up and Pull-Down Resistor Values. 9. The Signaling Environment. Point-to-Point Topology. Number of Devices. Signal Routing and Layout. Trace Impedance and Line Termination. Add-in Card Clock Skew Specifications. AGP Voltage Characteristics. Vref Generation. Component Pinout Recommendations. Motherboard/Add-in Card Interoperability. Pull-up/Pull-down Resistors. Maximum AC Ratings and Device Protection. Power Supply. Mechanicals. Connector Pinout. DC Specifications. 1x Transfer Mode Timing Parameters. 2x and 4x Transfer Mode Timing Model. Driver Characteristics. Receiver Characteristics. Changes to Clock Frequencies in Mobile Designs. 10. Intro To AGP Transfer Types. Command Types and the Transfer Length. AGP Ordering Rules. Fence Command. Flush Command. 11. AGP Arbitration. The AGP Arbiter. Maximizing Bus Usage via GNT# Pipelining. 12. AGP Request Transactions. Two Request Generation Mechanisms. AGP Request Queue Depth. Issuing Transaction Requests via AD and C/BE buses. Issuing Transaction Requests via the SBA Port. 13. AGP Data Flow Control. Introduction. In AGP, Data Is Transferred in Blocks. Wait State Before First Data Block. Inserting Wait States Between Blocks. Data Transfer Size Can Be Less Than a Data Block. Usage of Byte Enables. But Minimum Data Transaction Is One Clock Long. Three Times Where Data Transfer Can Be Delayed. AGP Adapter's Control of Data Transfers. North Bridge's Control of Data Transfers. RBF# Prevents Return of Low-Priority Read Data. 14. x Data Transactions. Introduction. General. Multiple Data Block Read Transaction. Multiple Block Read Data Transfer with Wait States. Read Data Transaction, Wait State Before First Block. Write Data Transaction, No Initial Wait State. Back-to-Back Write Data Transactions, No Delays. 15. x Data Transactions. Introduction. 2x Transfer Mode Data Transactions. Back-to-Back Read Transfers, No Wait States. Multiple Block Read, No Wait States. Multiple Block Write with Wait States. Back-to-Back Write Data Transactions, Minimum Delay. 16. x Data Transactions. Introduction. General. Using Strobe Falling-Edges To Latch Data. Using Strobe Crossover Point to Latch Data. Back-to-Back Read Data Transactions, No Wait States. Multiple Block Read, No Wait States. Multi-Block Read with Wait State Before 2nd Data Block. Back-to-Back Write Data Transactions, No Wait States. 17. Fast Write Transactions. Use of WBF# to Prevent Start of Fast Write. Arbitration to Perform a Fast Write. Introduction to the Fast Write Transaction. Fast Write Transactions in 2x Mode. Fast Write Transactions in 4x Mode. Adapter-Initiated Premature Transaction Termination. Master-Initiated Premature Transaction Termination. Back-to-Back Fast Write Transactions. Two Fast Write Transactions with No Idle in Between. Use of the WBF# Signal. Short, Fast Write Transactions and DEVSEL#. 18. Collision Avoidance. Many Transaction Pairs Require Turnaround Cycle(s). AGP Write Data Followed by Fast Write. AGP Write Data Followed by AGP Read Data. 19. AGP Pro. The Problem. AGP Pro Connector. Requires Two Adjacent PCI Connectors. High-Power AGP Pro Card. Low-Power AGP Pro Card. Card Power Indication. Power Usage. Index. 0201700697T04062001


MindShare, Inc. is one of the leading technical training companies in the hardware industry, providing innovative courses for dozens of companies, including Intel, IBM, and Compaq. David Dzatko has over ten years of experience designing and testing computer systems. He is currently an instructor with MindShare, Inc., teaching computer architecture to leading companies in the computer industry. Tom Shanley, president of MindShare, Inc., is one of the world's foremost authorities on computer system architecture. In the course of his career, he has trained thousands of engineers in hardware and software design. 0201700697AB07142003
EAN: 9780201700695
ISBN: 0201700697
Untertitel: Sprache: Englisch.
Erscheinungsdatum: Oktober 1999
Seitenanzahl: 400 Seiten
Format: kartoniert
Es gibt zu diesem Artikel noch keine Bewertungen.Kundenbewertung schreiben