Applied Formal Verification: For Digital Circuit Design

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Mai 2005



Formal verification is a powerful new digital design method. In this cutting-edge tutorial, two of the field's best known authors team up to show designers how to efficiently apply Formal Verification, along with hardware description languages like Verilog and VHDL, to more efficiently solve real-world design problems.
Contents: Simulation-Based Verification * Introduction to Formal Techniques * Contrasting Simulation vs. Formal Techniques * Developing a Formal Test Plan * Writing High-Level Requirements * Proving High-Level Requirements * System Level Simulation * Design Example * Formal Test Plan * Final System Simulation


<H4>PREFACE <H3>Chapter 1: Introduction to Verification <H3>Chapter 2: Verification Process <H3>Chapter 3: Current Verification Techniques <H3>Chapter 4: Introduction to Formal Techniques <H3>Chapter 5: Formal Basics and Definitions <H3>Chapter 6: Property Specification <H3>Chapter 7: The Formal Test Plan Process <H3>Chapter 8: Techniques for Proving Properties <H3>Chapter 9: Final System Simulation <H4>APPENDIX A: IEEE 1850 PSL PROPERTY SPECIFICATION LANGUAGE <H4>APPENDIX B: IEEE 1800 SYSTEM VERILOG ASSERTIONS <H4>BIBLIOGRAPHY <H4>INDEX


Douglas L. Perry is the Director of Marketing for Virtutech, Inc. He is the author of four editions of McGraw-Hill's VHDL. He lives in San Ramon, California. Harry D. Foster serves as Chairman of the Accellera Formal Verification Technical Committee, which is currently defining the PSL (Property Specification Language) standard. He is co-author of the new Kluwer Academic Publishers book Assertion-Based Design. The Chief Methodologist at Jasper Design, Mr. Foster formerly was Verplex Systems' Chief Architect. He lives in Richardson, Texas.
EAN: 9780071443722
ISBN: 007144372X
Untertitel: 'Electronic Engineering'. New. Sprache: Englisch.
Erscheinungsdatum: Mai 2005
Seitenanzahl: 240 Seiten
Format: gebunden
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